This first course in a series that extends over three consecutive terms is concerned with tailoring algorithms and with devising high performance hardware architectures for their implementation as ASIC or with FPGAs. The focus is on front end design using HDLs and automatic synthesis for producing industrial-quality circuits.

This second course in our VLSI series is concerned with how to turn digital circuit netlists into safe, testable and manufacturable mask layout, taking into account various parasitic effects. Starting in 2025, the course will rely on pre-dominantly open-source tools and put more emphasis on hands-on design. All students will be expected to complete their own design (in groups of two).

In this revamped course, we will concentrate on practical aspects of modern integrated circuit testing with an emphasis on hands-on-experience on an IC tester. This will help students to better understand several aspects that have been highlighted in previous VLSI lecture series and allow them to test their own ICs designed during prior semester/bachelor theses.