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227-0147-00L 6 Credits BSC , MSC D-ITET , D-INFK , D-PHYS
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VLSI 2: From Netlist to Complete System on Chip

Lecturers & Examiners: Frank Kagan Gürkaynak, Prof. Dr. Luca Benini
VVZ CR n/a

Last Updated: 2026-02-05 16:38:15

Abstract

This second course in our VLSI series is concerned with how to turn digital circuit netlists into safe, testable and manufacturable mask layout, taking into account various parasitic effects. Low-power circuit design is another important topic. Economic aspects and management issues of VLSI projects round off the course.

Objective

Know how to design digital VLSI circuits that are safe, testable, durable, and make economic sense.

Content

The second course begins with a thorough discussion of various technical aspects at the circuit and layout level before moving on to economic issues of VLSI. Topics include: - The difficulties of finding fabrication defects in large VLSI chips. - How to make integrated circuit testable (design for test). - Synchronous clocking disciplines compared, clock skew, clock distribution, input/output timing. - Synchronization and metastability. - CMOS transistor-level circuits of gates, flip-flops and random access memories. - Sinks of energy in CMOS circuits. - Power estimation and low-power design. - Current research in low-energy computing. - Layout parasitics, interconnect delay, static timing analysis. - Switching currents, ground bounce, IR-drop, power distribution. - Floorplanning, chip assembly, packaging. - Layout design at the mask level, physical design verification. - Electromigration, electrostatic discharge, and latch-up. - Models of industrial cooperation in microelectronics. - The caveats of virtual components. - The cost structures of ASIC development and manufacturing. - Market requirements, decision criteria, and case studies. - Yield models. - Avenues to low-volume fabrication. - Marketing considerations and case studies. - Management of VLSI projects. Exercises are concerned with back-end design (floorplanning, placement, routing, clock and power distribution, layout verification). Industrial CAD tools are being used.

Resources

Lecture Notes

H. Kaeslin: "Top-Down Digital VLSI Design, from Gate-Level Circuits to CMOS Fabrication", Lecture Notes Vol.2 , 2015.All written documents in English.

Literature

H. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.

Learning Materials (Links)

General Information

Language
English
Levels
BSC , MSC
Frequency
Yearly recurring

Examination

Type
session examination
Mode
written 180 minutes
Aids
Student's own hand-written summary, 6 single-sided A4 papers. No electronic help, no photocopies or printouts of any form, for summary preparation. No calculators or communication devices.
Prüfungsaufgaben werden in Englisch vorgegeben, Antworten auf Deutsch oder Englisch akzeptiert.

Course Components

Type Title Time & Place Hours
lecture with exercise VLSI 2: From Netlist to Complete System on Chip
Lecture: Tuesday, 14:00 - 16:00 Exercises: Wednesday, 09:00 - 12:00
  • Tue 14:15-16:00 (HG D 1.2)
  • Tue 14:15-16:00 (LFW B 1)
  • Wed 09:15-12:00 (ETZ D 61.1)
  • Wed 09:15-12:00 (ETZ D 61.2)
  • Wed 09:15-12:00 (ETZ D 96.1)
5 h weekly

Offered In