VVZ API is not affiliated with ETH Zurich. Data might be outdated or incorrect. Please view the official ETHZ Vorlesungsverzeichnis for binding information.

227-0147-00L 6 Credits BSC , MSC D-ITET , D-PHYS , D-INFK
You're viewing possible stale or outdated data. Please check the latest semester for more up-to-date information.

VLSI 2: From Netlist to Complete System on Chip

VVZ CR n/a

Last Updated: 2026-06-01 11:33:22

Abstract

This second course in our VLSI series is concerned with how to turn digital circuit netlists into safe, testable and manufacturable mask layout, taking into account various parasitic effects. Starting in 2025, the course will rely on pre-dominantly open-source tools and put more emphasis on hands-on design. All students will be expected to complete their own design (in groups of two).

Objective

- Understand how VLSI circuits are designed - Gain practical experience in IC Design using open source tools - Qualify to take part in semester/master theses that involve practical IC Design - Develop your own System-on-Chip based on the examples in exercises

Content

The course begins with an overview refresher on front-end design (HDL, Synthesis) and then covers - Basic manufacturing steps - Standard cells, routing layers - Floorplanning, I/O ring, packaging - Timing in IC design and clock dsirtribution - Parasitic effects in IC Design - Placement and routing - Power analysis - Testing of IC circuits - Assessing the performance of ICs. The most important part of the lecture is that the exercises, which will make use of open-source tools (as much as possible) and work on a System-On-Chip design. The exercises are essential for the lecture as the grading will be done based on a project based on the exercises.

Resources

Lecture Notes

Course www site:http://vlsi.ethz.chH. Kaeslin: "Top-Down Digital VLSI Design, from Gate-Level Circuits to CMOS Fabrication", Lecture Notes Vol.2 , 2015.All written documents in English.

Literature

H. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.

Learning Materials (Links)

General Information

Language
English
Levels
BSC , MSC
Frequency
Yearly recurring

Examination

Type
graded semester performance
Students will be asked to complete their own System-On-Chip design with an improvement based on the example design used in exercises, and they will be graded on the quality/timeliness of the design.As the final project is based on the exercises, we strongly suggest that students visit all exercises.The students will work in groups of 1 or 2 people, they will take the exercise design, and will be given a larger area to make one addition/improvement in the design. Submissions will be made electronically, grade will depend on timeliness (respecting the submission deadlines), functionality, performance and originality.Up to 5 best designs will be actually fabricated.

Registration & Places

Max Places
72

Course Components

Type Title Time & Place Hours
lecture with exercise VLSI 2: From Netlist to Complete System on Chip
Lecture: Tuesday, 14:00 - 16:00 Exercises: Wednesday, 09:00 - 12:00
  • Tue 14:15-16:00 (LFW B 1)
  • Wed 09:15-12:00 (ETZ D 61.1)
  • Wed 09:15-12:00 (ETZ D 61.2)
5 h weekly

Offered In