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VLSI I: from Architectures to Very Large Scale Integration Circuits and FPGAs
VLSI I: von Architektur zu hochintegrierter Schaltung und FPGA
Last Updated: 2026-02-05 15:10:12
Abstract
Know how Very-Large-Scale Integration and VLSI architecture relate to each other.Become fluent in front-end design from a block diagram to gate-level netlists. How to model digital ICs with VHDL., write testbenches, and synthesize gate-level netlists for ASICs and FPGAs.
Objective
Know how Very-Large-Scale Integration and VLSI architecture relate to each other. Become fluent in front-end design from conceiving a block diagram to synthesizing a gate-level netlist. Gain practical experience with VHDL, with simulation, and with automatic synthesis of digital integrated circuits.
Content
This course is concerned with system-level issues of VLSI design and FPGA implementations: Terminology, overview on design methodologies and fabrication depths, levels of abstraction for circuit modelling, VLSI design flow, dedicated VLSI architectures, how to obtain an architecture for a given processing algorithm, architectural transformations for meeting throughput, area, and power requirements. Hardware Description Languages (HDL) and the underlying concepts, VHDL (IEEE std. 1076) for simulation and synthesis, the IEEE-1164 logic system, Register Transfer Level (RTL) synthesis. Timing models, Anceau diagrams, functional verification of digital circuits, reusable testbenches, building blocks of digital VLSI circuits, case studies of actual circuits, comparison with microprocessors and DSPs. During the exercises, students learn how to model digital ICs with VHDL. They write testbenches for simulation purposes and synthesize gate-level netlists for ASICs and FPGAs.
Resources
Lecture Notes
yes, in English.
General Information
- Language
- German
- Frequency
- Yearly recurring
Examination
- Type
- session examination
- Mode
- written 180 minutes
- Aids
- 1 Blatt A4 beidseitig von Hand beschriftet, keine Vervielfältigungen.
Course Components
| Type | Title | Time & Place | Hours |
|---|---|---|---|
| lecture with exercise |
VLSI I: von Architektur zu hochintegrierter Schaltung und FPGA
Vorlesung beginnt am Di der 1. Semesterwoche.
Danach Vorlesung am Fr, Uebung am Di.
|
|
5 h weekly |
Offered In
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6. Semester (Die Studierenden im MS-Programm haben freie Auswahl aus dem Angebot der Kernfächer)
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