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227-0116-00L 7 Credits BSC , DS , MSC D-ITET , D-INFK , D-PHYS , D-MATH
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VLSI I: from Architectures to VLSI Circuits and FPGAs

VLSI I: von Architektur zu hochintegrierter Schaltung und FPGA

Lecturers & Examiners: Prof. em. Dr. Wolfgang Fichtner, Dr. Norbert Felber, Prof. em. Dr. Hubert Kaeslin
VVZ CR 4.53

Last Updated: 2026-02-05 15:19:51

Abstract

Understand Application-Specific Integrated Circuits (ASIC) and Field-Programmable Gate-Arrays (FPGA). Become fluent in front-end design of Very-Large-Scale Integrated circuits (VLSI chips) from architecture design to gate-level netlists. How to model digital circuits with VHDL, write testbenches, and synthesize gate-level netlists for ASICs and FPGAs.

Objective

Understand Application-Specific Integrated Circuits (ASIC) and Field-Programmable Gate-Arrays (FPGA). Know their organization and be able to identify suitable application areas. Become fluent in front-end design of Very-Large-Scale Integrated circuits (VLSI chips) from architecture design to gate-level netlists. How to model digital circuits with VHDL, write testbenches, and synthesize gate-level netlists for ASICs and FPGAs. Gain practical experience with the hardware description language VHDL, with simulation, and with automatic synthesis of digital integrated circuits.

Content

This course is concerned with system-level issues of VLSI design and FPGA implementations: Terminology, overview on design methodologies and fabrication depths, levels of abstraction for circuit modelling, VLSI design flow, dedicated VLSI architectures, how to obtain an architecture for a given processing algorithm, architectural transformations for meeting throughput, area, and power requirements. Hardware Description Languages (HDL) and the underlying concepts, VHDL (IEEE std. 1076) for simulation and synthesis, the IEEE-1164 logic system, Register Transfer Level (RTL) synthesis. Timing models, Anceau diagrams, functional verification of digital circuits, reusable testbenches, building blocks of digital VLSI circuits, case studies of actual circuits, comparison with microprocessors and DSPs. During the exercises, students learn how to model digital ICs with VHDL. They write testbenches for simulation purposes and synthesize gate-level netlists for ASICs and FPGAs.

Resources

Lecture Notes

yes, in English.

General Information

Language
German
Levels
BSC , DS , MSC
Frequency
Yearly recurring

Examination

Type
session examination
Mode
written 180 minutes
Aids
1 Blatt A4 beidseitig von Hand beschriftet, keine Vervielfältigungen.

Course Components

Type Title Time & Place Hours
lecture with exercise VLSI I: von Architektur zu hochintegrierter Schaltung und FPGA
Vorlesung beginnt am Mittwoch der 1. Semesterwoche Danach Vorlesung am Freitag, Übungen am Mittwoch
  • Fri 10:15-12:00 (ETZ E 6)
  • 21.03 Date 10:15-12:00 (ETZ E 9)
  • 28.03 Date 09:15-12:00 (ETZ F 91)
  • 28.03 Date 09:15-12:00 (ETZ K 91)
  • 04.04 Date 09:15-12:00 (ETZ F 91)
  • 04.04 Date 09:15-12:00 (ETZ K 91)
  • 23.05 Date 09:15-12:00 (ETZ F 91)
  • 23.05 Date 09:15-12:00 (ETZ K 91)
5 h weekly

Offered In