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VLSI III: Fabrication and Verification
VLSI III: Fabrikation und Verifikation hochintegrierter Schaltungen
Last Updated: 2026-02-05 14:57:26
Objective
Know-how of methods, software tools and equipment for testable design of VLSI circuits, sound verification of the silicon, and physical analysis in case of faulty semiconductor devices. Knowledge of modern semiconductor technologies
Content
Whereas the preceding courses deal with design aspects of VLSI circu-its, this one addresses manufacturing, testing, physical analysis, and packaging issues, such as: Effects of fabrication defects, abstraction from physical to transistor- and gate-level fault models, fault grading of large ASICs. Generation of efficient test vector sets, enhancement of testability by built-in self test techniques. Modern IC testers: Architectures and application. Deep-submicron CMOS fabrication processes with multi metal levels and the physical analysis of their devices. Packaging problems and solutions. Technology outlook. Exercises teach students how to use CAE/CAD software and automatic test equipment for verifying ASICs after fabrication. Students that submitted a design for manufacturing at the end of the 7th semester do so on their own circuits. Physical analysis methods with professional equipment (AFM, DLTS) complement this training.
Resources
Lecture Notes
yes
General Information
- Language
- German
- Frequency
- Yearly recurring
Examination
- Type
- session examination
- Mode
- oral 30 minutes
Course Components
| Type | Title | Time & Place | Hours |
|---|---|---|---|
| lecture with exercise |
VLSI III: Fabrikation und Verifikation hochintegrierter Schaltungen
Übungen gemäss Einschreibeliste
|
|
4 h weekly |