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VLSI II: Design of Highly Integrated Circuits
VLSI II: Entwurf von hochintegrierten Schaltungen
Last Updated: 2026-02-05 14:55:15
Abstract
"VLSI II: Design of Highly Integrated Circuits" covers all aspects of digital ASIC design from a synthesis model to mask layout. Also dealt with are VLSI economics and project management.The student works through seven practical exercises that cover the complete VLSI backend design flow using industrial CAD tools.The nominal workload is 100 hours not including exam preparation.
Objective
To know how to design digital VLSI circuits at the logic, circuit, and physical level.
Content
The second course begins with a thorough discussion of various technical aspects at the circuit and layout level. It then moves on to economic issues of VLSI. Topics include: limitations of functional design verification, design for test. Evaluation of various synchronous clocking disciplines and clock distribution techniques. Metastability and synchronization. Cell libraries, construction of CMOS gates, flip-flops and memories. Power estimation and low-power design. Layout parasitics, transport delay, switching currents, ground bounce, ESD and latch-up, power distribution, floorplanning, chip assembly. Layout design at the mask level. Timing verification, physical design verification. Cost structures of microelectronics design and fabrication, avenues to low-volume fabrication, virtual components, management of VLSI projects.
Resources
Lecture Notes
English lecture notes
General Information
- Language
- German
- Frequency
- Yearly recurring
Examination
- Type
- session examination
- Mode
- oral 30 minutes
Course Components
| Type | Title | Time & Place | Hours |
|---|---|---|---|
| lecture with exercise | VLSI II: Entwurf von hochintegrierten Schaltungen |
|
5 h weekly |