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VLSI I: from Architectures to Highly-Integrated Circuits and FPGAs
VLSI I: von Architektur zu hochintegrierter Schaltung und FPGA
Last Updated: 2026-02-05 14:55:36
Objective
Know-how on the relationship between Very-Large-Scale Integration and VLSI architecture. Gain practical experience with VHDL and automatic synthesis of digital circuits.
Content
This course is mainly concerned with system-level issues of VLSI, and circuit design as far as required for FPGA implementations: Terminology, overview on design methodologies and fabrication avenues, levels of abstraction used for circuit description and simulation, VLSI design flow, dedicated VLSI architectures, how to obtain an architecture for a given processing algorithm, architectural transformations for meeting throughput, area, and power requirements. Hardware Description Languages (HDL) and their underlying concepts, VHDL for simulation and synthesis, the IEEE-1164 logic system, Register Transfer Level (RTL) synthesis. Timing models, Anceau diagrams, functional verification of digital circuits and systems, building blocks of digital VLSI circuits, case studies of actual circuits, comparison with microprocessors and DSPs. During the exercises students learn how to model digital ICs with VHDL. They write testbenches for simulation purposes and synthesize gate-level netlists for ASICs and FPGAs.
Resources
Lecture Notes
yes
General Information
- Language
- German
- Frequency
- Yearly recurring
Examination
- Type
- session examination
- Mode
- oral 30 minutes
Course Components
| Type | Title | Time & Place | Hours |
|---|---|---|---|
| lecture with exercise | VLSI I: von Architektur zu hochintegrierter Schaltung und FPGA |
|
5 h weekly |