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VLSI II: Design of Very Large Scale Integration Circuits
VLSI II: Entwurf von hochintegrierten Schaltungen
Last Updated: 2026-02-05 15:24:43
Abstract
"VLSI II: Design of Very Large Scale Integration Circuits" covers all aspects of digital ASIC design from a synthesis model to mask layout. Also dealt with are VLSI economics and project management.The student works through seven practical exercises that cover the complete VLSI backend design flow using industrial CAD tools.The nominal workload is 100 hours not including exam preparation.
Objective
Know how to design digital VLSI circuits that are safe, testable and make sense economically.
Content
The second course begins with a thorough discussion of various technical aspects at the circuit and layout level before moving on to economic issues of VLSI. Topics include: limitations of functional design verification, design for test. Evaluation of various synchronous clocking disciplines, clock distribution, input/output timing. Synchronization and metastability. Cell libraries, construction of CMOS gates, flip-flops and memories. Power estimation and low-power design. Static timing analysis. Layout parasitics, transport delay, switching currents, ground bounce, power distribution. Floorplanning, chip assembly, packaging, layout design at the mask level, physical design verification. Electromigration, electrostatic dischrage, and latch-up. Cost structures of microelectronics design and fabrication, avenues to low-volume fabrication, virtual components, management of VLSI projects.
Resources
Lecture Notes
English lecture notes (Dr. N. Felber).
Literature
"Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication" Cambridge University Press, 2008, ISBN 9780521882675 (Dr. H. Kaeslin).
General Information
- Language
- German
- Levels
- DS , MSC , WBZ
- Frequency
- Yearly recurring
Examination
- Type
- session examination
- Mode
- oral 30 minutes
Course Components
| Type | Title | Time & Place | Hours |
|---|---|---|---|
| lecture with exercise | VLSI II: Entwurf von hochintegrierten Schaltungen |
|
5 h weekly |
Offered In
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Communication (A total of 42 CP must be achieved during the Master Program. The individual study plan is subject to the tutor's approval.)
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Core Subjects (These core subjects are particularly recommended for the field of "Communications".)
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Micro- and Optoelectronics (A total of 42 CP must be achieved during the Master Program. The individual study plan is subject to the tutor's approval.)
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Core Subjects (These core subjects are particularly recommended for the field of "Micro- and Optoelectronics".)
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