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VLSI 2: From Netlist to Complete System on Chip
Last Updated: 2026-07-21 00:35:27
Abstract
This second course in our VLSI series is concerned with how to turn digital circuit netlists into safe, testable and manufacturable mask layout, taking into account various parasitic effects. Starting in 2025, the course will rely on pre-dominantly open-source tools and put more emphasis on hands-on design. All students will be expected to complete their own design (in groups of two).
Objective
- Understand how VLSI circuits are designed - Gain practical experience in IC Design using open source tools - Qualify to take part in semester/master theses that involve practical IC Design - Develop your own System-on-Chip based on the examples in exercises
Content
The course begins with an overview refresher on front-end design (HDL, Synthesis) and then covers - Basic manufacturing steps - Standard cells, routing layers - Floorplanning, I/O ring, packaging - Timing in IC design and clock dsirtribution - Parasitic effects in IC Design - Placement and routing - Power analysis - Testing of IC circuits - Assessing the performance of ICs. The most important part of the lecture is that the exercises, which will make use of open-source tools (as much as possible) and work on a System-On-Chip design. The exercises are essential for the lecture as the grading will be done based on a project based on the exercises.
Resources
Lecture Notes
Course www site:http://vlsi.ethz.chH. Kaeslin: "Top-Down Digital VLSI Design, from Gate-Level Circuits to CMOS Fabrication", Lecture Notes Vol.2 , 2015.All written documents in English.
Literature
H. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.