VLSI 5: Design of a Standard-Cell Library

Abstract

This fifth course in our VLSI lecture series consolidates the theoretical and practical knowledge from the courses VLSI 1, VLSI 2, and VLSI 3, offering hands-on experience in designing and characterizing a standard-cell library for integration into a standard digital integrated circuit design flow.

Objective

By the end of this course, students will be able to: - design their own standard-cell library - characterize standard cells in terms of functionality, timing, power, and area - generate the files (such as LIB, LEF, and SPICE files) required by a standard-cell library - perform synthesis and automated place-and-route using their own standard-cell library - assess the performance of a given standard-cell library through benchmark designs - optimize an existing standard-cell library with respect to specific design goals, such as area, power, throughput, and/or reliability

Content

The fifth course in the VLSI series is composed of three phases. The first phase consists of lectures that review the fundamentals of standard-cell design and introduce the concepts behind standard-cell characterization. The second phase consists of tutorials that teach the students how to characterize standard cells and how to incorporate the resulting files into CAD software for digital integrated circuit design. The third phase consists of a project in which the students individually design and characterize their own standard cells to collectively create a standard-cell library that will be evaluated using several benchmark designs. Throughout the three phases of the course, the following topics will be covered: - Standard-cell design - Alternative logic styles - Layout design and parasitics - Advanced delay models - Characterizing timing and power - Understanding LIB, LEF, and SPICE files - Performing synthesis with Synopsys DC using a custom standard-cell library - Performing automated place-and-route with Cadence Innovus using a custom standard-cell library - Performing signoff checks with Siemens Calibre for a design containing custom standard cells The lecture and tutorial phases will take place during the first half of the semester. The class time of the second half of the semester (the third phase) is dedicated for the students to design, characterize, and benchmark their standard cells. During the last lecture, the students will present their individual project results. Students that deliver a satisfactory presentation and a satisfactory short report (5-10 pages), together with their design files, will pass the course. Please note that the tutorials and project of this class are extensive and time consuming. While a significant amount of class time is dedicated to both the tutorials and project, expect to spend around three additional hours per week of your own time to complete these tasks. It is possible to turn in the final project report and design files until the end of July.

Resources