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Synthesis of Digital Circuits
Last Updated: 2026-06-03 00:14:20
Abstract
This course covers theoretical and practical aspects of hardware compilation and synthesis. It provides a comprehensive view into the design flow of digital circuits and presents algorithms, tools, and methods to generate digital circuits from high-level descriptions. It discusses recent advancements and current challenges of high-level synthesis (HLS) for FPGAs.
Objective
The goal of this course is to provide students with an in-depth understanding of the hardware design process and hardware compilation techniques. The students will learn how to differentiate software and hardware design models. They will be able to apply high-level synthesis (HLS) concepts to design hardware from software specifications. They will be able to contrast various HLS methods, assess the area-performance tradeoffs of different HLS solutions, and identify challenges and limitations of current FPGA-oriented HLS approaches.
Content
The course will cover the following topics: - Hardware design flow and introduction to high-level synthesis (HLS) - Static code analysis and optimization - Classic scheduling algorithms (e.g., ASAP, ALAP, List scheduling) - Classic sharing and binding algorithms (e.g., Left-edge algorithm) - Pipelining and SDC modulo scheduling - Polyhedral code analysis and optimization - FPGA logic synthesis, placement, and routing - Applications of HLS for FPGAs - Challenges of modern HLS for FPGAs - Recent HLS advancements and alternative HLS approaches The course will be divided into two main blocks. The first block will consist of classical lectures, accompanied by exercises. The second block will interleave lectures with: (1) practical work that will introduce students to a standard HLS flow for FPGAs and (2) student presentations of recent research topics on HLS and FPGA design.
Resources
Lecture Notes
Lecture notes will be provided on the course website.
Literature
Literature will be provided on the course website.
General Information
- Language
- English
- Levels
- MSC
- Frequency
- Yearly recurring
Examination
- Type
- graded semester performance
Course Components
| Type | Title | Time & Place | Hours |
|---|---|---|---|
| lecture | Synthesis of Digital Circuits |
|
2 h weekly |
| exercise | Synthesis of Digital Circuits |
|
2 h weekly |
Offered In
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Track: Communication (The core courses and specialization courses below are a selection for students who wish to specialize in the area of "Communication", see . The individual study plan is subject to the tutor's approval.)
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Specialization Courses (These specialization courses are particularly recommended for the area of "Communication", but you are free to choose courses from any other field in agreement with your tutor. Semester / Research Projects are not allowed in this category. A minimum of 40 credits must be obtained from specialization courses during the Master's Programme.)
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Track: Computers and Networks (The core courses and specialization courses below are a selection for students who wish to specialize in the area of "Computers and Networks", see . The individual study plan is subject to the tutor's approval.)
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Specialization Courses (These specialization courses are particularly recommended for the area of "Computers and Networks", but you are free to choose courses from any other field in agreement with your tutor. Semester / Research Projects are not allowed in this category. A minimum of 40 credits must be obtained from specialization courses during the Master's Programme.)
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Electives (This is a selection of courses particularly suitable for the MSc QE. In agreement with the tutor, students may choose other courses from the ETH course catalogue.)
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