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P&S: Memory Design: From Architecture down to Basic Cells
Last Updated: 2026-06-03 00:14:20
Abstract
The category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.
Objective
Memories are important components in all modern electronic devices, e.g. computers, smartphones, or tablets. Depending on their specialization, engineers look at memories from a different perspective. This P&S will give you an overview of these different perspectives, which do not only exist for memories, but in general for all integrated circuits. In particular, during this P&S you will get familiar with state-of-the-art computer-aided design tools. Among them are highly sophisticated programs used by engineers active in the research and development units of large semiconductor companies. The P&S "Memory Design: From Architecture down to Basic Cells" consists of three parts of approximately equal length, each of them corresponding to a different perspective on memories: 1. System design: In this part you will get to know different memory types from a system developer's point of view. What are they capable of? How are they incorporated into circuits to create a storage system that can provide the right size and speed with an acceptable power consumption? A simple cache simulator will be used to study the influence of various design parameters on the memory hierarchy. Participants will study specific memory types in small groups and discuss them with the P&S partners during a presentation. 2. Circuit design: In this part the emphasis will be on how memories can be realized as electronic circuits. How should transistors be connected to each other to write, store, and read data? How should these transistors be sized to achieve the desired speed or power efficiency? With simulations you will experience how engineers design and optimize such circuits. 3 Physical Design: This part will go one step further. Millions of transistors on a small silicon die are at the core of modern memory chips. How are the memory cells on the chip manufactured? How does a memory cell look like? How is the memory cell optimized? You will learn about the design process with the help of modern simulation tools that are nowadays used in industry. You will also learn about the methods and technologies to produce modern integrated circuits. This P&S will only take place if 12 students register. Course participation is mandatory after registration.
General Information
- Language
- English
- Levels
- BSC
- Frequency
- Yearly recurring
Examination
- Type
- ungraded semester performance
Registration & Places
- Signup Start
- 13.02.2026
- Signup End
- 27.02.2026
Course Components
| Type | Title | Time & Place | Hours |
|---|---|---|---|
| practical/laboratory course |
P&S: Memory Design: From Architecture down to Basic Cells
Für den Zugang zum Angebot und zur Einschreibung loggen Sie sich hier ein (mit Ihrem n.ETHZ account):
Bitte beachten Sie, dass die Seite jeweils erst zwei Wochen vor Semesterbeginn zugänglich ist und im Verlauf des Semesters wieder abgeschaltet wird. Die Einschreibung ist nur von Freitag vor Semesterbeginn bis zum ersten Freitagmittag im Semester möglich.
To access the offer and to enroll for courses log in (with your n.ethz account):
Please note that the P&S-site is accessible no earlier than two weeks before the start of the semester until four weeks after the start of the semester. Enrollment is only possible from Friday before the start of the semester until noon of the first Friday in the semester.
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3 h weekly |
Offered In
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Laboratory Courses, Projects, Seminars (A minimum of 15 cp must be achieved in the category "Laboratory Courses, Projects, Seminars")
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Projects & Seminars (only for BSc EEIT) (Enrolment is only possible for students in the BSc Electrical Engineering and Information Technology, from Friday before the start of the semester. Places are allocated using the P&S application tool ( ). For more offers, see "Projects & Seminars (open to all)".)
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