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P&S: From Software Applications to FPGA Designs
Last Updated: 2026-06-01 11:31:03
Abstract
The category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.
Objective
Field Programmable Gate Arrays (FPGAs) are reconfigurable hardware devices that can be programmed into application‐specific accelerators, achieving high performance and energy efficiency. Recently, FPGAs have been customized for large-scale AI applications, integrated into data centers to process massive data, and packaged with processors for high parallelism. However, FPGAs are notoriously difficult to use: their programming traditionally requires writing tedious, error-prone, and time-consuming low-level hardware description languages (e.g., VHDL, Verilog). In contrast, High‐Level Synthesis (HLS) tools enable programmers to automatically generate hardware designs from high‐level software abstractions (e.g., C/C++), thus enabling designers to quickly and effortlessly create FPGA designs. Still, HLS must be guided by appropriate code restructuring and annotations to achieve good-quality FPGA implementations. This course aims to provide students with practical skills for FPGA programming using HLS. Students will learn about the FPGA design flow, employ HLS to create FPGA designs from software specifications, and apply code optimizations to achieve efficient FPGA implementations of real-life applications. In the course, the students will perform the following tasks: - Complete a series of guided practical assignments to familiarize themselves with FPGA design using HLS. - Apply HLS to create a functional but unoptimized FPGA implementation of a real-life workload (e.g., a signal processing algorithm). - Learn to reason about different hardware design metrics (e.g., memory hierarchy and bandwidth, spatial and temporal parallelism, area-performance tradeoffs). - Apply diverse HLS optimizations to achieve the desired area/performance objectives. - Implement, optimize, and evaluate a real-life workload on an FPGA using HLS. The course will be taught in English. In addition to the 3-hour weekly sessions with the teaching assistants, the students will work independently on improving their algorithms and implementing them on an FPGA. This is estimated to take an additional 3 hours per week. The course requires only a basic understanding of digital circuit design, computer architecture, and C/C++ programming. A background in FPGA design is not required.
General Information
- Language
- English
- Levels
- BSC
- Frequency
- Yearly recurring
Examination
- Type
- ungraded semester performance
Registration & Places
- Signup Start
- 12.09.2025
- Signup End
- 26.09.2025
Course Components
| Type | Title | Time & Place | Hours |
|---|---|---|---|
| practical/laboratory course |
P&S: From Software Applications to FPGA Designs
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To access the offer and to enroll for courses log in (with your n.ethz account):
Please note that the P&S-site is accessible no earlier than two weeks before the start of the semester until four weeks after the start of the semester. Enrollment is only possible from Friday before the start of the semester until noon of the first Friday in the semester.
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3 h weekly |
Offered In
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Praktika, Projekte, Seminare (Es müssen mindestens 15 KP aus der Kategorie "Praktika, Projekte, Seminare" erworben werden.)
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Projekte & Seminare (nur für BSc EEIT) (Die Belegung ist ausschliesslich für Studierende im BSc Elektrotechnik und Informationstechnologie ab Freitag vor Semesterbeginn möglich. Plätze werden über das P&S-Bewerbungstool ( ) zugeteilt. Siehe weitere Angebote unter "Projekte & Seminare (offen für alle)".)
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