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227-0146-00L 6 Credits DR , MSC D-ITET , D-ERDW , D-MAVT , D-PHYS
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Data Conversion System Design

Up until HS23 named Analog-to-Digital Converters
VVZ CR n/a

Last Updated: 2026-06-01 11:30:56

Abstract

This course provides a thorough treatment of integrated data conversion systems from system level specifications and trade-offs, over architecture choice down to circuit implementation.

Objective

Data conversion systems are substantial sub-parts of many electronic systems, e.g. the audio conversion system of a home-cinema systems or the base-band front-end of a wireless modem. Data conversion systems usually determine the performance of the overall system in terms of dynamic range and linearity. Students will learn the underlying principles of data conversion and be introduced to the different methods and circuit architectures to implement such a conversion. The conversion methods such as successive approximation or algorithmic conversion are explained based on their operation principle accompanied with the appropriate mathematical calculations, including effects of non-idealties in some cases. After successful completion of the course students should understand the concept of an ideal ADC, know all major converter architectures, their principle of operation and what governs their performance.

Content

- Introduction: examples of data conversion architectures; information representation; abstraction, categorization and symbolic representation; basic conversion algorithms; data converter application; tradeoffs among key parameters; ADC taxonomy. - Dual-slope & successive approximation register (SAR) converters: dual slope principle & converter; SAR ADC operating principle; SAR implementation with a capacitive array; range extension with segmented array. - Algorithmic & pipelined A/D converters: algorithmic conversion principle; sample & hold stage; pipe-lined converter; multiplying DAC; flash sub-ADC and n-bit MDAC; redundancy for correction of non-idealties, error correction. - Performance metrics and non-linearity: ideal ADC; offset, gain error, differential and integral non-linearities; capacitor mismatch; impact of capacitor mismatch on SAR ADC's performance. - Flash, folding an interpolating analog-to-digital converters: flash ADC principle, thermometer to binary coding, sparkle correction; limitations of flash converters; the folding principle, residue extraction; folding amplifiers; cascaded folding; interpolation for folding converters; cascaded folding and interpolation. - Noise in analog-to-digital converters: types of noise; noise calculation in electronic circuit, kT/C-noise, sampled noise; noise analysis in switched-capacitor circuits; aperture time uncertainty and sampling jitter. - Delta-sigma A/D-converters: linearity and resolution; from delta-modulation to delta-sigma modulation; first-oder delta-sigma modulation, circuit level implementation; clock-jitter & SNR in delta-sigma modulators; second-order delta-sigma modulation, higher-order modulation, design procedure for a single-loop modulator. - Digital-to-analog converters: introduction; current scaling D/A converter, current steering DAC, calibration for improved performance, delta-sigma D/A-converters.

Resources

Lecture Notes

Slides are available online underhttps://iis-students.ee.ethz.ch/lectures/analog-to-digital-converters/

Literature

- B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1994 - M. Gustavsson et. al., CMOS Data Converters for Communications, Springer, 2010 - R.J. van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, Springer, 2010

Learning Materials (Links)

General Information

Language
English
Levels
DR , MSC
Frequency
Yearly recurring

Examination

Type
session examination
Mode
oral 30 minutes

Course Components

Type Title Time & Place Hours
lecture Data Conversion System Design
  • Tue 10:15-12:00 (ETZ E 7)
2 h weekly
exercise Data Conversion System Design
  • Wed 16:15-18:00 (ETZ D 61.2)
  • Wed 16:15-18:00 (ETZ J 91)
2 h weekly

Offered In