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263-3504-00L 2 Credits MSC , WBZ D-ITET , D-INFK , D-MATH
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Hardware Acceleration for Data Processing

Lecturers & Examiners: Dr. Michael Joseph Giardino, Prof. Dr. Michal Friedman
The deadline for deregistering expires at the end of the second week of the semester. Students who are still registered after that date, but do not attend the seminar, will officially fail the seminar.
VVZ CR n/a

Last Updated: 2026-06-01 11:30:47

Abstract

The seminar will cover topics related to data processing using new hardware in general and hardware accelerators (GPU, FPGA, specialized processors) in particular.

Objective

The seminar will cover topics related to data processing using new hardware in general and hardware accelerators (GPU, FPGA, specialized processors) in particular.

Content

The general application areas are big data and machine learning. The systems covered will include systems from computer architecture, high performance computing, data appliances, and data centers.

Resources

Learning Materials (Links)

General Information

Language
English
Levels
MSC , WBZ
Frequency
Yearly recurring

Examination

Type
graded semester performance
The deadline for deregistering expires at the end of the second week of the semester. Students who are still registered after that date, but do not attend the seminar, will officially fail the seminar.

Registration & Places

Max Places
24
Priority: Registration for the course unit is only possible for the primary target group

Course Components

Type Title Time & Place Hours
seminar Hardware Acceleration for Data Processing
  • Mon 14:15-16:00 (CHN D 46)
2 h weekly

Offered In