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P&S: FPGA-based Exploration of DRAM and RowHammer
Last Updated: 2026-02-05 16:14:44
Abstract
The category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.
Objective
DRAM is predominantly used to build the main memory systems of modern computing devices. To improve the performance, reliability, and security of DRAM, it is critical to perform experimental characterization and analysis of existing cutting-edge DRAM chips. SoftMC is an FPGA-based DRAM testing infrastructure that enables the programmer to perform all low-level DRAM operations (i.e., DDR commands) in a cycle-accurate manner. SoftMC provides a simple and intuitive high-level programming interface (in C++) that completely hides the low-level details of the FPGA from programmers. Programmers implement test routines in C++, and the test routines automatically get translated into the low-level SoftMC memory controller operations in the FPGA. SoftMC developers write low-level hardware description language code to enable new and faster studies. In this P&S, you will have the chance to learn how DRAM is organized and operates in a low-level and gain practical experience in using SoftMC while developing SoftMC programs for new DRAM characterization studies related to performance, reliability, and security. You may also improve the SoftMC infrastructure itself to enable new studies. And, who knows, you might discover new security vulnerabilities like RowHammer. This will be the right P&S for you if you are interested in DRAM technology and would like to learn more about it as well as FPGA technology and how it can be used for practical purposes such as understanding and mitigating RowHammer attacks, generating true random numbers, reducing memory latency, fingerprinting and identifying devices, and improving reliability. Prerequisites of the course: - Digital Circuits AND Computer Engineering (or equivalent courses) - Familiarity with FPGA programming - Interest in low-level system exploration and memory - Interest in discovering why things do or do not work and solving problems The course is conducted in English.
Resources
Lecture Notes
See:https://safari.ethz.ch/projects_and_seminars/doku.php?id=softmc
Literature
Learning Materials: =================== - An old version of SoftMC is here: https://github.com/CMU-SAFARI/SoftMC - SoftMC description: https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf - SoftMC lecture: https://www.youtube.com/watch?v=tnSPEP3t-Ys - Example RowHammer study using SoftMC: https://people.inf.ethz.ch/omutlu/pub/Revisiting-RowHammer_isca20.pdf - Example security attack study using SoftMC: Link - Example neural network acceleration study using SoftMC: Link - Example random number generation study using SoftMC: Link - Example physical unclonable function study using SoftMC: https://people.inf.ethz.ch/omutlu/pub/dram-latency-puf_hpca18.pdf - The original RowHammer study using SoftMC: https://people.inf.ethz.ch/omutlu/pub/dram-row-hammer_isca14.pdf - PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM: https://arxiv.org/abs/2111.00082 - PiDRAM Source Code: https://github.com/CMU-SAFARI/PiDRAM - DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips: https://arxiv.org/pdf/2211.05838.pdf - DRAM Bender Source Code: https://github.com/CMU-SAFARI/DRAM-Bender
General Information
- Language
- English
- Levels
- BSC
- Frequency
- Semesterly recurring
Examination
- Type
- ungraded semester performance
Registration & Places
- Signup Start
- 15.09.2023
- Signup End
- 29.09.2023
Course Components
| Type | Title | Time & Place | Hours |
|---|---|---|---|
| practical/laboratory course |
P&S: FPGA-based Exploration of DRAM and RowHammer
Für den Zugang zum Angebot und zur Einschreibung loggen Sie sich hier ein (mit Ihrem n.ETHZ account):
Bitte beachten Sie, dass die Seite jeweils erst zwei Wochen vor Semesterbeginn zugänglich ist und im Verlauf des Semesters wieder abgeschaltet wird. Die Einschreibung ist nur von Freitag vor Semesterbeginn bis zum ersten Freitagmittag im Semester möglich.
To access the offer and to enroll for courses log in (with your n.ethz account):
Please note that the P&S-site is accessible no earlier than two weeks before the start of the semester until four weeks after the start of the semester. Enrollment is only possible from Friday before the start of the semester until noon of the first Friday in the semester.
Time: To be arranged with each student
Location: various
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No time listed | 3 h weekly |
Offered In
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Laboratory Courses, Projects, Seminars (A minimum of 15 cp must be achieved in the category "Laboratory Courses, Projects, Seminars)
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Projects & Seminars (Enrolment is only possible for students in the BSc Electrical Engineering and Information Technology from Friday before the start of the semester. Places are allocated using the P&S application tool ( ). Please only enrol for P&S for which you apply via the tool.)
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