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227-0128-00L 4 Credits MSC D-ITET

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Synthesis of Digital Circuits

Lecturers & Examiners: Prof. Dr. Lana Josipovic

VVZ CR 3.8

Last Updated: 2026-02-05 16:21:46

Abstract

This course covers theoretical and practical aspects of hardware compilation and synthesis. It provides a comprehensive view into the design flow of digital circuits and presents algorithms, tools, and methods to generate digital circuits from high-level descriptions. It discusses recent advancements and current challenges of high-level synthesis for FPGAs.

Objective

The goal of this course is to provide students with an in-depth understanding of the hardware design process and hardware compilation techniques. The students will learn how to differentiate software and hardware design models. They will be able to apply high-level synthesis concepts to design hardware from software specifications. They will be able to contrast various HLS methods, assess the area-performance tradeoffs of different HLS solutions, and identify challenges and limitations of current FPGA-oriented HLS approaches.

Content

The course will cover the following topics: - Hardware design flow and introduction to high-level synthesis (HLS) - Static code analysis and optimization - Classic HLS algorithms for scheduling (e.g., ASAP, ALAP, List scheduling) - Classic HLS algorithms for sharing and binding (e.g., Left-edge algorithm) - Pipelining and SDC modulo scheduling - Polyhedral code analysis and optimization - Applications of HLS for FPGAs - Challenges of modern HLS for FPGAs - Recent HLS advancements and alternative HLS approaches The course will be divided into two main blocks. The first block will consist of classical lectures, accompanied by exercises. The second block will interleave lectures with: (1) practical work that will introduce students to a standard HLS flow for FPGAs and (2) student presentations of recent research topics on HLS and FPGA design.

Resources

Lecture Notes

Lecture notes will be provided on the course website.

Literature

Literature will be provided on the course website.

General Information

Language: English
Levels: MSC
Frequency: Yearly recurring

Examination

Type: graded semester performance

The grade is composed out of:- a written midterm exam, covering the theoretical topics of the first course block- individual practical assignments, graded based on the correctness of the produced results and an oral discussion of the solution- paper review and presentation, graded based on review quality (e.g., clarity of the paper summary, critical analysis of its advantages and shortcomings), presentation quality (e.g., language, writing style), and oral discussion

Course Components

Type	Title	Time & Place	Hours
lecture	Synthesis of Digital Circuits	Wed 13:15-15:00 (ETZ G 91)	2 h weekly
exercise	Synthesis of Digital Circuits	Wed 15:15-16:00 (ETZ G 91) 05.04 Date 13:15-16:00 (HG E 1.1) 31.05 Date 10:15-12:00 (ETZ G 91)	1 h weekly

Offered In

Electrical Engineering and Information Technology Master
- Master Studies (Programme Regulations 2018)
  - Communication (The core courses and specialization courses below are a selection for students who wish to specialize in the area of "Communication", see . The individual study plan is subject to the tutor's approval.)
    - Specialization Courses (These specialization courses are particularly recommended for the area of "Communication", but you are free to choose courses from any other field in agreement with your tutor. A minimum of 40 credits must be obtained from specialization courses during the Master's Programme.)
- Master Studies (Programme Regulations 2008)
  - Major Courses (A total of 42 CP must be achieved form courses during the Master Program. The individual study plan is subject to the tutor's approval.)
    - Communication
      - Recommended Subjects (These courses are recommended, but you are free to choose courses from any other special field. Please consult your tutor.)