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Projekte & Seminare: Intelligent Architectures via Hardware/Software Cooperation
Last Updated: 2026-02-05 16:07:20
Abstract
The category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.
Objective
Modern general-purpose processors are agnostic to an application’s high-level semantic information. Hence, they employ prediction-based techniques to enable computational and memory optimizations, such as prefetching, cache management policies, memory data placement, instruction scheduling, and many others. As such, the potential of such optimizations is limited due to the limited information the underlying hardware can discover on its own and such optimizations come with large area, power and complexity overheads required by the hardware for prediction purposes. Purely-hardware optimizations cannot achieve their performance potential and waste power, complexity and hardware area, since they are not aware of the application characteristics. On the other hand, purely-software optimizations are fundamentally tied up and limited by the underlying hardware. A promising way to increase the performance of modern applications is to co-design software and hardware. Hence, lately both industry and academia are making serious attempts to improve performance, energy and security using hardware/software cooperative schemes such as application-specific hardware accelerators (e.g., Google’s Tensor Processing Unit) and application-specific extensions in general-purpose processors (e.g., Media Engine in Apple M1). In this course, we will explore several different topics around hardware/software co-design such as: (i) new hardware/software interfaces (e.g., virtual memory, instruction set architecture) to enhance performance, energy and security, (ii) hardware/software co-design schemes to improve the performance of the memory subsystem in killer memory-intensive applications (e.g., sparse and irregular workloads), (iii) hardware/software cooperative machine-learning-based techniques for different microarchitectural components such as prefetchers, caches and branch predictors, which would continuously learn from the vast amount of memory accesses seen by a processor and adapt to the varying workload and system conditions. If you are enthusiastic about working hands-on to design both software and hardware, this is your P&S. You will have the opportunity to study modern applications, propose software changes to better match the underlying hardware components, design new hardware components that better match the overlying software and come up with new machine-learning techniques to design efficient microarchitectural components. You will also learn how to program industry-supported microarchitectural simulators and study the performance of modern workloads after your hardware/software modifications. Prerequisites of the course: - Digital Design and Computer Architecture (or equivalent course). - Familiarity with C/C++ programming and strong coding skills. - Interest in future computer architectures and computing paradigms. - Interest in discovering why things do or do not work and solving problems - Interest in making systems efficient and usable Preferable: - Hands-on experience with Machine Learning frameworks (depends on the topic you choose) The course is conducted in English.
General Information
- Language
- English
- Levels
- BSC
- Frequency
- Semesterly recurring
Examination
- Type
- ungraded semester performance
Registration & Places
- Signup Start
- 18.02.2022
- Signup End
- 04.03.2022
Course Components
| Type | Title | Time & Place | Hours |
|---|---|---|---|
| practical/laboratory course |
Projekte & Seminare: Intelligent Architectures via Hardware/Software Cooperation
Für den Zugang zum Angebot und zur Einschreibung loggen Sie sich hier ein (mit Ihrem n.ETHZ account):
Bitte beachten Sie, dass die Seite jeweils erst zwei Wochen vor Semesterbeginn zugänglich ist und im Verlauf des Semesters wieder abgeschaltet wird. Die Einschreibung ist nur von Freitag vor Semesterbeginn bis zum ersten Freitagmittag im Semester möglich.
To access the offer and to enroll for courses log in (with your n.ethz account):
Please note that the P&S-site is accessible no earlier than two weeks before the start of the semester until four weeks after the start of the semester. Enrollment is only possible from Friday before the start of the semester until noon of the first Friday in the semester.
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No time listed | 3 h weekly |
Offered In
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Laboratory Courses, Projects, Seminars (A minimum of 15 cp (under the 2018 regulations), respectively at least 18 cp (under the 2016 regulations) must be achieved in the category "Laboratory Courses, Projects, Seminars".)
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Projects & Seminars (Enrolment is only possible for students in the BSc Electrical Engineering and Information Technology from Friday before the start of the semester. Places are allocated using the P&S application tool ( ). Please only enrol for P&S for which you apply via the tool.)
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