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227-0085-35L 3 Credits BSC D-ITET

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Projects & Seminars: Enabling Secure, Reliable and Fast Memory with Hands-On FPGA Experiments

Projekte & Seminare: Enabling Secure, Reliable and Fast Memory with Hands-On FPGA Experiments

Lecturers & Examiners: Prof. Dr. Onur Mutlu

Only for Electrical Engineering and Information Technology BSc. The course unit can only be taken once. Repeated enrollment in a later semester is not creditable.

VVZ CR n/a

Last Updated: 2026-02-05 15:53:33

Abstract

The category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.

Objective

DRAM is predominantly used to build the main memory systems of modern computing devices. To improve the performance, reliability, and security of DRAM, it is critical to perform experimental characterization and analysis of existing cutting-edge DRAM chips. SoftMC is an FPGA-based DRAM testing infrastructure that enables the programmer to perform all low-level DRAM operations (i.e., DDR commands) in a cycle-accurate manner. SoftMC provides a simple and intuitive high-level programming interface (in C++) that completely hides the low-level details of the FPGA from programmers. Programmers implement test routines in C++, and the test routines automatically get translated into the low-level SoftMC memory controller operations in the FPGA. SoftMC developers write low-level hardware description language code to enable new and faster studies. In this P&S, you will have the chance to learn how DRAM is organized and operates in a low-level and gain practical experience in using SoftMC while developing SoftMC programs for new DRAM characterization studies related to performance, reliability and security. You may also improve the SoftMC infrastructure itself to enable new studies. And, who knows, you might discover new security vulnerabilities like RowHammer. This will be the right P&S for you if you are interested in DRAM technology and would like to learn more about it as well as FPGA technology and how it can be used for practical purposes such as understanding and mitigating RowHammer attacks, generating true random numbers, reducing memory latency, fingerprinting and identifying devices, and improving reliability. Prerequisites of the course: - Digital Design and Computer Architecture (or equivalent course) - Familiarity with FPGA programming - Interest in low-level hacking and memory - Interest in discovering why things do or do not work and solving problems The course is conducted in English. Course website: https://safari.ethz.ch/projects_and_seminars/doku.php?id=softmc

General Information

Language: English
Levels: BSC
Frequency: Semesterly recurring

Examination

Type: ungraded semester performance

Registration & Places

Signup Start: 19.02.2021
Signup End: 05.03.2021

Course Components

Type	Title	Time & Place	Hours
practical/laboratory course	Projekte & Seminare: Enabling Secure, Reliable and Fast Memory with Hands-On FPGA Experiments Für den Zugang zum Angebot und zur Einschreibung loggen Sie sich hier ein (mit Ihrem n.ETHZ account): Bitte beachten Sie, dass die Seite jeweils erst zwei Wochen vor Semesterbeginn zugänglich ist und im Verlauf des Semesters wieder abgeschaltet wird. Die Einschreibung ist nur von Freitag vor Semesterbeginn bis zum ersten Freitagmittag im Semester möglich. To access the offer and to enroll for courses log in (with your n.ethz account): Please note that the P&S-site is accessible no earlier than two weeks before the start of the semester until four weeks after the start of the semester. Enrollment is only possible from Friday before the start of the semester until noon of the first Friday in the semester. Time: To be arranged with each student Location: various	No time listed	3 h weekly

Offered In

Electrical Engineering and Information Technology Bachelor
- Laboratory Courses, Projects, Seminars (A minimum of 18 cp must be obtained from the category "Laboratory Courses, Projects, Seminars".)
  - Projects & Seminars (A maximum of 13 cp can be obtained from Projects & Seminars. Each course can be registered for only once. Enrolment is only possible for students in the BSc Electrical Engineering and Information Technology from Friday before the start of the semester. Places are allocated using the P&S application tool ( ). Please only enrol for P&S for which you apply via the tool.)